1. Technical Field
The present invention relates to a sigma delta modulator, a fractional frequency synthesizer, and a sigma delta modulating method. More particularly, the present invention relates to a sigma delta modulator, a fractional frequency synthesizer, and a sigma delta modulating method for outputting an output signal obtained by performing sigma delta modulation on an input signal.
2. Related Art
There has been known a frequency synthesizer that includes a voltage controlled oscillator, a frequency divider, a phase comparator, and a low-pass filter and outputs an oscillation signal with a set frequency. Furthermore, there has been known a fractional frequency synthesizer that changes a division ratio of a frequency divider by means of an output signal from a sigma delta modulator having a plurality of accumulators (see Patent Documents 1 to 3, for example). The fractional frequency synthesizer can output an oscillation signal with a frequency that is expressed as a multiple of decimal precision of a reference clock frequency.
[Patent Document 1] Japanese Patent Application Publication 2004-260791
[Patent Document 2] Japanese Patent Application Publication 2001-298363
[Patent Document 3] U.S. Pat. No. 6,844,836 specification
Meanwhile, in the sigma delta modulator, an inclination of a noise shaping characteristic increases, and thus an amplitude of an output signal becomes large when increasing the number of stages of accumulators. Therefore, in the fractional frequency synthesizer using the sigma delta modulator with the accumulators of many stages, a variation region of a division ratio increases, and thus a phase error between a frequency-dividing signal and a reference clock becomes large.
As a result having a growing phase error, the fractional frequency synthesizer including the sigma delta modulator with the accumulators of many stages is influenced by a linearity of a phase comparator, and on the contrary noises in the vicinity of a frequency of an oscillation signal become large.